Semiconductor devices are continuously scaling down with the development of the semiconductor manufacture technology, and requirements on manufacture techniques for semiconductor devices are becoming higher and higher.
At present, the development of semiconductor manufacture technology has been achieved mainly by continually shortening the channel length of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), while the shortening of the channel length is achieved mainly by improving the semiconductor process techniques and raising the processing levels. Although the channel length has already been shortened to level of deep sub-micron and even nanometer, further shortening of the channel length is limited by many factors. On one hand, the improvement in the semiconductor processing techniques can hardly meet the needs of semiconductor manufacture; on the other hand, the physical performances of the devices also incur many problems, for example, Short-Channel Effects, DIBL (Drain-Induced Barrier Lowering) effects, too high threshold voltages, etc.
Therefore, adopting new materials, developing new processes, and building new device structures have become common goals in the semiconductor industry for further development of semiconductor manufacture technology. It has been fully accepted nowadays that a technical measure for effectively improving the physical performances of devices is to improve the mobility of carriers. The mobility of carriers is an important physical quantity indicating the moving speeds of carriers under electric field, the magnitude of which directly influences the operating frequencies and speeds of the semiconductor devices and circuits.
In the present mainstream technology, the carrier mobility is increased mainly through etching trenches in a substrate on both sides of the channel region and epitaxially growing strained source/drain regions in the trenches. For example, with respect to an nMOSFET, source and drain regions with a tensile stress are usually formed on both sides of the channel region by epitaxially growing Si:C with a certain percentage of C, so as to apply a tensile stress to the two sides of the channel; and with respect to a pMOSFET, the source and drain regions are formed by epitaxially growing SiGe with a certain percentage of Ge, so as to apply a compressive stress to the two sides of the channel.
However, such a method for forming source/drain regions cannot sufficiently increase the carrier mobility and improve the performances of the channel region. Hence, it is desirable to provide a novel semiconductor device structure and a method for manufacturing the same to improve the device performances.